1. Field of the Invention
The present invention relates to technology concerned with a semiconductor device and a method of manufacturing the same, and in particular, to technology effective for application to a method of manufacturing a semiconductor device having a nonvolatile memory capable of electrically programming and erasing.
2. Description of the Related Art
There has been known the so-called flash memory capable of bulk erasing among semiconductor devices having a nonvolatile memory capable of electrically programming and erasing. Because the flash memory excels in portability and impact resistance, and is capable of electrically bulk erasing, there has been a rapid increase in demand for it as a memory device for use in a personal digital assistant such as a portable personal computer, digital still camera, and so forth in recent years. Reduction in bit cost, due to contraction in memory cell area, is an important factor for achieving expansion of its market, and as described in, for example, “Applied Physics” issued by the Society of Applied Physics, Vol. 65, No. 11, Nov. 10, 1996, pp. 1114–1124, there have since been proposed various memory cell schemes intended to attain such a purpose.
Further, for example, virtual ground memory cells using three-layered polysilicon gates are disclosed in JP, 2694618, B. That is, this memory cells each have semiconductor regions and three gates, formed in a well of a semiconductor substrate. The three gates include a floating gate formed on top of the well, a control gate formed so as to extend over the well and the floating gate, and an erase gate formed between the control gate and the floating gate, adjacent to each other. The three gates are made of polysilicon, and are isolated from each other by an insulator film, respectively, the floating gate being also isolated from the well. The control gate is connected to control gates adjacent thereto so as to be aligned in the direction of row lines, constituting a word line. This is a virtual ground memory cell array wherein source and drain diffusion layers are formed so as to be aligned in the direction of column lines, orthogonal to the direction of the row lines, and the diffusion layers are in common use with adjacent memory cells. By so doing, relaxation of pitches in the direction of the column lines is aimed at. The erase gate is disposed so as to be parallel with a channel as well as the word line between adjacent word lines (control gates).
As tasks to be tackled, in common with all those memory cells, there can be cited the following problems attributable to the fact that a repetition pattern of isolation regions and channel regions tends to have narrower pitches as a result of reduction in memory cell size. First, the formation of the isolation regions at narrower pitches will result in occurrence of large stress in the course of oxidation processes such as gate oxidation of surrounding transistors, gate oxidation of the floating gates of memory cells, and so forth, so that quality deficiencies occur to a substrate, leading to occurrence of a leak between the source and the drain of transistors to thereby create a cause for malfunction. Further, a gate oxide cannot be formed to a uniform thickness due to stress, resulting in occurrence of a problem such as a kink to the volt-ampere characteristic of the transistors, and so forth. Still further, not only the upper surface of the substrate but also sidewall faces thereof undergo oxidation at the time of the gate oxidation, so that the channel width of the transistor will be reduced, thereby disabling the transistor to obtain sufficient current.
As a stack-type flash memory technology developed to solve those problems described above, there has been reported, for example, a technology whereby shallow groove isolation are formed by use of floating gates as a mask. Adverse effects of stress occurring at the time of the gate oxidation can be avoided by forming the gate oxide prior to the formation of the shallow groove isolation.
Now, in contrast to the stack-type flash memory cell, a split-gate memory cell, which is another type of memory cell, has many advantages in that programming is executed by injecting channel-hot-electrons generated on the source side, and faster program speed and program operation at lower power consumption can be implemented by taking advantage of a high injection efficiency. However, when down-sizing the split-gate memory cell as well, there naturally exists the problem associated with the formation of the shallow groove isolation at narrow pitches.